Median architecture by accumulative parallel counters

Download

[thumbnail of APCMedian-TCAS-Centaur.pdf]

Preview

Text - Accepted Version
· Please see our End User Agreement before downloading. | Preview

Advice

Please see our End User Agreement.

It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.

Tools

Lists

Cadenas Medina, J., Megson, G. M. and Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445 (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747 doi: 10.1109/TCSII.2015.2415655

Abstract/Summary

The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

Altmetric Badge

Item Type	Article
URI	https://reading-clone.eprints-hosting.org/id/eprint/36577
Identification Number/DOI	10.1109/TCSII.2015.2415655
Refereed	Yes
Divisions	Life Sciences > School of Biological Sciences > Department of Bio-Engineering
Uncontrolled Keywords	Median Filter, Pipelined Processing, Image Processing.
Publisher	IEEE
Download/View statistics	View download statistics for this item

Download Statistics

Downloads

Downloads per month over past year

Deposit Details

Date Deposited:	16 Mar 2015 15:42	Date item deposited into CentAUR
Last Modified:	22 Dec 2024 05:28	Date item last modified

References

[1] S. G. Akl, The Design and Analysis of Parallel Algorithms. Englewood Cliffs, NJ: Prentice-Hall, 1989, pp. 39–58. [2] T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, Introduction to Algorithms. Cambridge, Mass., MIT Press, 2003. [3] D. Prokin and M. Prokin, “Low hardware complexity pipelined rank filter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 446–450, June 2010. [4] R. D. Chen, P. Y. Chen, and C. H. Yeh, “Design of an area-efficient one-dimensional median filter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 662–666, Oct. 2013. [5] R. D. Chen, P. Y. Chen, and C. H. Yeh, “A low-power architecture for the design of a one-dimensional median filter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, to appear, 2015. [6] J. Cadenas, G. M. Megson, R. S. Sherratt, and P. Huerta, “Fast median calculation method,” Electron. Lett., vol. 48, no. 10, pp. 558-560, May 2012. [7] B. Parhami and C. H. Yeh, “Accumulative parallel counters,” in Proc. 23rd Asilomar Conf. on Signals, Systems, and Computers, 1995, pp. 513–516. [8] M. A. Neilsen and I. L. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000. [9] J. F. Wakerly, Digital Design: Principles and Practices. 4th Ed., Upper Saddle River, NJ: Prentice-Hall, 2006, Ch. 6. [10] Q. Gan, J. M. P. Langlois, and Y. Savaria, “Parallel array histogram architecture for embedded implementations,” Electron. Lett., vol. 49, no. 2, pp. 99-101, Jan. 2013. [11] Hieu B. V., Beak S. Choi S, Seon J. and Jeong T. T.: ‘Thermometer-to-binary encoder with bubble error correction (BEC) for flash analog-to-digital converters (FADC)’, in Proc. 3rd Int. Conf. on Communications and Electronics, 2010, pp. 102-106. [12] S. Perreault and P. Hebert, “Median filtering in constant time,” IEEE Trans. Image Process., vol. 16, no. 9, pp. 2389-2394, Sept. 2007. [13] B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs. New York, NY: Oxford University Press, 2000, pp. 125-140.

University Staff: Request a correction | Centaur Editors: Update this record

Search Google Scholar