C-slow retimed parallel histogram architectures for consumer imaging devices

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[1] H.-C. Huang, F.-C. Chang and W.-C. Fang, “Reversible data hiding with histogram-based difference expansion for QR code applications,” IEEE Trans. Consumer Electron., vol. 57, no. 2, pp. 779-787, May 2011. [2] J. O. Cadenas, R. S. Sherratt, P. Huerta and W. C. Kao, “Parallel pipelined arrays for real-time histogram computation in consumer devices,” IEEE Trans. Consumer Electron., vol. 57, no. 4, pp. 1460-1464, Nov. 2011. [3] K. Yoon, C. Kim, B. Lee and D. Lee, “Single-chip CMOS image sensor for mobile applications,” IEEE J. on Solid State Circuits, vol. 37, no. 12, pp. 1839-1845, Dec. 2002. [4] J. O. Cadenas, R. S. Sherratt, P. Huerta, and W. C. Kao, “Parallel pipelined histogram architecture via C-slow retiming,” IEEE Int. Conf. on Consumer Electronics, 2013, accepted. [5] C. Leiserson, F. Rose and J. Saxe, “Optimizing synchronous circuits by retiming,” 3rd Caltech Conf. on VLSI, 1993. [6] N. Weaver and J. Wawarzynek, “The effects of datapath placement and C-slow retiming on three computational benchmarks,” 10th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, 2002, pp. 303-313. [7] R. S. Sherratt and Oswaldo Cadenas, “A double data rate architecture for OFDM based wireless consumer devices,” IEEE Trans. Consumer Electron., vol. 56, no. 1, pp. 23-26, Feb. 2010. [8] Xilinx, Inc., “Virtex-6 Family Overview,” DS150 (v2.4) January 19, 2012.