Parallel pipelined histogram architecture via c-slow retiming

Cadenas Medina, J., Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P., Kao, W. C. and Megson, G. M. (2013) Parallel pipelined histogram architecture via c-slow retiming. In: Proceedings of the 2013 IEEE International Conference on Consumer Electronics (ICCE). IEEE, pp. 230-231. ISBN 9781467313612 doi: 10.1109/ICCE.2013.6486871

Abstract/Summary

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

Additional Information	Paper originally presented at IEEE International Conference on Consumer Electronics, Las Vegas, USA, Jan 2013
Item Type	Book or Report Section
URI	https://reading-clone.eprints-hosting.org/id/eprint/32267
Identification Number/DOI	10.1109/ICCE.2013.6486871
Refereed	Yes
Divisions	Life Sciences > School of Biological Sciences > Department of Bio-Engineering
Additional Information	Paper originally presented at IEEE International Conference on Consumer Electronics, Las Vegas, USA, Jan 2013
Publisher	IEEE
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