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de Dinechin, F., Manjunathaiah, M., Risset, T. and Spivey, M. (2004) Design of highly parallel architecture with Alpha and Handel. In: Villar, E. and Mermet, J. (eds.) System Specification and Design Languages: Best of FDL '02. The ChDL Series, 4. Kluwer Academic Publishers, Boston, pp. 293-302. ISBN 140207414X doi: 10.1007/0-306-48734-9_24
Abstract/Summary
We propose a bridge between two important parallel programming paradigms: data parallelism and communicating sequential processes (CSP). Data parallel pipelined architectures obtained with the Alpha language can be embedded in a control intensive application expressed in CSP-based Handel formalism. The interface is formally defined from the semantics of the languages Alpha and Handel. This work will ease the design of compute intensive applications on FPGAs.
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| Additional Information | Presented at 5th Forum on Specification and Design Languages (FDL)MARSEILLE, FRANCE, SEP 17-24, 2002 |
| Item Type | Book or Report Section |
| URI | https://reading-clone.eprints-hosting.org/id/eprint/16304 |
| Identification Number/DOI | 10.1007/0-306-48734-9_24 |
| Refereed | No |
| Divisions | Science > School of Mathematical, Physical and Computational Sciences > Department of Computer Science No Reading authors. Back catalogue items |
| Uncontrolled Keywords | data parallelism, communicating sequential processes, FPGA, hardware compiling |
| Additional Information | Presented at 5th Forum on Specification and Design Languages (FDL)MARSEILLE, FRANCE, SEP 17-24, 2002 |
| Publisher | Kluwer Academic Publishers |
| Download/View statistics | View download statistics for this item |
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